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| UTI760A RTS Remote Terminal for Stores FEATURES E Complete MIL-STD-1760A Notice I through III E E E E E E E remote terminal interface 1K x 16 of on-chip static RAM for message data, completely accessible to host Self-test capability, including continuous loop-back compare Programmable memory mapping via pointers for efficient use of internal memory, including buffering multiple messages per subaddress RT-RT Terminal Address Compare Command word stored with incoming data for enhanced data management User selectable RAM Busy (RBUSY) signal for slow or fast processor interfacing Full military operating temperature range, -55C to +125C, screened to the specific test methods listed in E Table I of MIL-STD-883, Method 5004, Class B, also Standard Military Drawing available Available in 68-pin pingrid array package INTRODUCTION The UT1760A RTS is a monolithic CMOS VLSI solution to the requirements of the dual-redundant MIL-STD-1553B interface as specified by MIL-STD-1760A. Designed to reduce cost and space in the mission stores interface, the RTS integrates the remote terminal logic with a userconfigured 1K x 16 static RAM. In addition, the RTS has a flexible subsystem interface to permit use with most processors or controllers. The RTS provides all protocol, data handling, error checking, and memory control functions, as well as comprehensive self-test capabilities. The RTS's memory meets all of a mission store's message storage needs through user-defined memory mapping. This memory-mapped architecture allows multiple message buffering at MCSA(4:0) MODE CODE/ SUBADDRESS OUTPUT MULTIPLEXING AND SELF-TEST WRAPAROUND LOGIC RTA(4:0) REMOTE TERMINAL ADDRESS CONTROL INPUTS OUT STATUS OUTPUTS DECODER COMMAND RECOGNITION CONTROL AND ERROR LOGIC 1K X 16 RAM ADDR(9:0) MUX ENCODER PTR REGISTER CLOCK AND RESET 12MHz LOGIC RESET 2MHz Figure 1. UT1760A RTS Functional Block Diagram IN OUT DECODER IN DATA(15:0) RTS-1 Table of Contents 1.0 ARCHITECTURE AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Memory Map and Host Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 RTS RAM Pointer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.3 Internal Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.4 Mode Code and Subaddress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.5 MIL-STD-1760A Subaddress and Mode Code Definitions . . . . . . . . . . . . . . . 9 1.6 Terminal Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.7 Internal Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.8 Power-up and Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.9 Encoder and Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.10 RT-RT Transfer Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.11 Illegal Command Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 MEMORY MAP EXAMPLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 PIN IDENTIFICATION AND DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . .16 MAXIMUM AND RECOMMENDED OPERATING CONDITIONS22 DC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 AC ELECTRICAL CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 PACKAGE OUTLINE DRAWING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.0 3.0 4.0 5.0 6.0 7.0 RTS-2 1.0 ARCHITECTURE AND OPERATION The UT1760A RTS is an interface device linking a MILSTD-1553 serial data bus and a host microprocessor system. The RTS's MIL-STD-1553B interface includes encoding/ decoding logic, error detection, command recognition, 1K x 16 of SRAM, pointer registers, clock, and reset circuits. Illegal subaddress circuitry makes the RTS MIL-STD1760A-specific. to its own internal RAM, it asserts the RBUSY signal to alert the host. The RBUSY signal is programmable via the internal Control Register to be asserted either 5.7ms or 2.7ms prior to the RTS needing access to its internal RAM. The RTS stores MIL-STD-1760A messages in 1K x 16 of on-chip RAM. For efficient use of the 1K x 16 memory on the RTS, the host programs a set of pointers to map where the 1760A message is stored. The RTS uses the upper 64 words (address 3C0 (hex) through 3FF (hex)) as pointers. The RTS provides pointers for all 30 receive subaddresses, all 30 transmit subaddresses, and four mode code commands with associated data words as defined in MIL-STD-1553B. The remaining 960 words of memory contain receive, transmit, and mode code data in a host-defined structure. 1.1 Memory Map and Host Memory Interface The host can access the 1K x 16 RAM memory like a standard RAM device through the 10-bit address and 16-bit data buses. The host uses the Chip Select (CS), Read/Write (RD/WR), and Output Enable (OE) signals to control data transfer to and from memory. When the RTS requires access RTS Memory Map Message Storage Locations 000 (hex) 3BF(hex) 15 MSB 0 LSB Receive Message Pointers (3C1 TO 3DE) XMIT VECTOR WORD MODE CODE (W/DATA) RCV SUBADDRESS 01 3C0 (hex) 3C1 (hex) RCV SUBADDRESS 30 SYNCHRONIZE MODE CODE (W/DATA) 15 MSB 0 LSB 3DE (hex) 3DF (hex) Transmit Message Pointers (3E1 TO 3FE) XMIT LAST COMMAND MODE CODE (W/DATA) XMT SUBADDRESS 01 3E0 (hex) 3E1 (hex) XMT SUBADDRESS 30 XMT BIT WORD MODE CODE (W/DATA) 15 MSB Figure 2. RTS Memory Map 0 LSB 3FE (hex) 3FF (hex) RTS-3 MESSAGE INDEX 15 (MSB) Message Index: Defines the maximum messages buffered for the given subaddress. 10 9 MESSAGE DATA ADDRESS 0 (LSB) Message Data Address: Indicates the starting memory address for incoming message storage. Figure 3. Message Pointer Structure 1.2 RTS RAM Pointer Structure The RAM 16-bit pointers have a 6-bit index field and a 10-bit address field. The 6-bit index field allows for the storage of up to 64 messages per subaddress. A message consists of the 1553 command word and its associated data words. The 16-bit pointer for Transmit Last Command Mode Code is located at memory location 3E0 (hex). The Transmit Last Command Mode Code pointer buffers up to 63 command words. An example of command word storage follows: Example: 3E0 (hex) Contents = FC00 (hex) 11 1111 00 0000 0000 Address Field = 000 (hex) Index Field = 3F (hex) First command word storage location (3E0 = F801): Address Field = 001 (hex) Index Field = 3E (hex) Sixty-third command word storage location (3E0 = 003F): Address Field = 03F (hex) Index Field = 00 (hex) Sixty-fourth command word storage location (3E0 = 003F) (previous command word overwritten): Address Field = 03F (hex) Index Field = 00 (hex) The Transmit Last Command Mode Code has Address Field boundary conditions for the location of command word buffers. The host can allocate a maximum 63 sequential locations following the Address Field starting address. For proper operation, the Address Field must start on an I x 40 (hex) address boundary, where I is greater than or equal to zero and less than or equal to 14. A list of valid Index and Address Fields follows: I 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Valid Index Fields 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) 3F (hex) to 00 (hex) Valid Address Fields 000 (hex) to 03F(hex) 040 (hex) to 07F (hex) 080 (hex) to 0BF(hex) 0C0 (hex) to 0FF (hex) 100 (hex) to 13F (hex) 140 (hex) to 17F (hex) 180 (hex) to 1BF (hex) 1C0 (hex) to 1FF (hex) 200 (hex) to 23F (hex) 240 (hex) to 27F (hex) 280 (hex) to 2BF (hex) 2C0 (hex) to 2FF (hex) 300 (hex) to 33F (hex) 340 (hex) to 37F (hex) 380 (hex) to 3BF (hex) RTS-4 Subaddress/Mode Code Transmit Vector Word Mode Code Receive Subaddress 01 Receive Subaddress 02 Receive Subaddress 03 Receive Subaddress 04 Receive Subaddress 05 Receive Subaddress 06 Receive Subaddress 07 Receive Subaddress 08 Receive Subaddress 09 Receive Subaddress 10 Receive Subaddress 11 Receive Subaddress 12 Receive Subaddress 13 Receive Subaddress 14 Receive Subaddress 15 Receive Subaddress 16 Receive Subaddress 17 Receive Subaddress 18 Receive Subaddress 19 Receive Subaddress 20 Receive Subaddress 21 Receive Subaddress 22 Receive Subaddress 23 Receive Subaddress 24 Receive Subaddress 25 Receive Subaddress 26 Receive Subaddress 27 Receive Subaddress 28 Receive Subaddress 29 Receive Subaddress 30 Synchronize w/Data Word Mode Code RAM Location 3C0 (hex) 3C1 (hex) 3C2 (hex) 3C3 (hex) 3C4 (hex) 3C5 (hex) 3C6 (hex) 3C7 (hex) 3C8 (hex) 3C9 (hex) 3CA (hex) 3CB (hex) 3CC (hex) 3CD (hex) 3CE (hex) 3CF (hex) 3D0 (hex) 3D1 (hex) 3D2 (hex) 3D3 (hex) 3D4 (hex) 3D5 (hex) 3D6 (hex) 3D7 (hex) 3D8 (hex) 3D9 (hex) 3DA (hex) 3DB (hex) 3DC (hex) 3DD (hex) 3DE (hex) 3DF (hex) Subaddress/Mode Code Transmit Last Command Mode Code Transmit Subaddress 01 Transmit Subaddress 02 Transmit Subaddress 03 Transmit Subaddress 04 Transmit Subaddress 05 Transmit Subaddress 06 Transmit Subaddress 07 Transmit Subaddress 08 Transmit Subaddress 09 Transmit Subaddress 10 Transmit Subaddress 11 Transmit Subaddress 12 Transmit Subaddress 13 Transmit Subaddress 14 Transmit Subaddress 15 Transmit Subaddress 16 Transmit Subaddress 17 Transmit Subaddress 18 Transmit Subaddress 19 Transmit Subaddress 20 Transmit Subaddress 21 Transmit Subaddress 22 Transmit Subaddress 23 Transmit Subaddress 24 Transmit Subaddress 25 Transmit Subaddress 26 Transmit Subaddress 27 Transmit Subaddress 28 Transmit Subaddress 29 Transmit Subaddress 30 Transmit Bit Word Mode Code RAM Location 3E0 (hex) 3E1 (hex) 3E2 (hex) 3E3 (hex) 3E4 (hex) 3E5 (hex) 3E6 (hex) 3E7 (hex) 3E8 (hex) 3E9 (hex) 3EA (hex) 3EB (hex) 3EC (hex) 3ED (hex) 3EE (hex) 3EF (hex) 3F0 (hex) 3F1 (hex) 3F2 (hex) 3F3 (hex) 3F4 (hex) 3F5 (hex) 3F6 (hex) 3F7 (hex) 3F8 (hex) 3F9 (hex) 3FA (hex) 3FB (hex) 3FC (hex) 3FD (hex) 3FE (hex) 3FF (hex) 1.3 Internal Registers The RTS uses two internal registers to allow the host to control the RTS operation and monitor its status. The host uses the Control (CTRL) signal along with Chip Select (CS), Read/Write (RD/WR), and Output Enable (OE) to read the 16-bit Status Register or write to the 13-bit Control Register. No address data is needed to select a register. The Control Register toggles bits in the MIL-STD-1553B status word, enables the biphase inputs, recognizes broadcast commands, selects Notice I and II or III, determines RAM Busy (RBUSY) timing, selects disconnect or terminal active flag, and puts the part in self-test mode. The Status Register supplies operational status of the UT1760A RTS to the host. These registers must be initialized before attempting RTS operation. Internal registers can be accessed while RBUSY is active. RTS-5 Control Register (Write Only) The 13-bit write-only Control Register manages the operation of the RTS. Write to the Control Register by applying a logic one to OE, and a logic zero to CTRL, CS, and RD/WR. Data is loaded into the Control Register via I/O pins DATA(12:0). Control register write must occur 50ns before the rising edge of COMSTR to latch data into the outgoing status word. Bit Number Bit 0 Bit 1 Bit 2 Bit 3 Initial Condition [1] [1] [0] [1] Description Channel A Enable. A logic 1 enables Channel A biphase inputs. Channel B Enable. A logic 1 enables Channel B biphase inputs. Terminal Flag. A logic 1 sets the Terminal Flag bit of the Status Word. System Busy. A logic 1 sets the Busy bit of the Status Word and limits RTS access to the memory. No data word can be retrieved or stored; command words will be stored. Bit 4 [0] Subsystem Busy. A logic 1 sets the Subsystem Flag bit of the Status Word. Bit 5 [0] Self-Test Channel Select. This bit selects which channel the self-test checks; a logic 1 selects Channel A and a logic 0 selects Channel B. Bit 6 [0] Self-Test Enable. A logic 1 places the RTS in the internal self-test mode and inhibits normal operation. Channels A and B should be disabled if self-test is chosen. Bit 7 [0] Service Request. A logic 1 sets the Service Request bit of the Status Word. Bit 8 [0] Instrumentation. A logic 1 sets the Instrumentation bit of the Status Word. Bit 9 [1] Broadcast Enable. A logic 1 enables the RTS to recognize broadcast commands. Bit 10 [1] Notice Select. A logic 1 enables Notice III operation; logic 0 enables Notice I or II operation. Bit 11 [1] DSCNCT/TERACT Pin Select. A logic 1 selects the "Disconnect" function; a logic 0 selects the "Terminal Active" function. Bit 12 [1] RBUSY Time Select. A logic 1 selects a 5.7s RBUSY alert; a logic 0 selects a 2.7s RBUSY alert. [] - Values in parentheses indicate the initialized values of these bits. CONTROL REGISTER (WRITE ONLY): X X X RBUSY PS TS [1] MSB [ ] defines reset state [1] NO TICE [1] BCEN INS SRQ ITST ITCS SUBS BUSY TF [1] [0] [0] [0] [0] [0] [1] [0] CH B CH A EN EN [1] [1] LSB Figure 4a. Control Register RTS-6 Status Register (Read Only): The 16-bit read-only Status Register provides the RTS system status. Read the Status Register by applying a logic 0 to CTRL, CS, and OE, and a logic 1 to RD/WR. The 16-bit contents of the Status Register are read from data I/O pins DATA(15:0). Bit Number Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Initial Condition [0] [0] [0] [0] [0] [0] Description MCSA0. The LSB of the mode code or subaddress as indicated by the logic state of bit 5. MCSA1. Mode code or subaddress as indicated by the logic state of bit 5. MCSA2. Mode code or subaddress as indicated by the logic state of bit 5. MCSA3. Mode code or subaddress as indicated by the logic state of bit 5. MCSA4. Mode code or subaddress as indicated by the logic state of bit 5. MC/SA. A logic 1 indicates that bits 4 through 0 are the subaddress of the last command word, and that the last command word was a normal transmit or receive command. A logic 0 indicates that bits 4 through 0 are a mode code, and that the last command was a mode command. Bit 6 [1] Channel A/B. A logic 1 indicates that the most recent command arrived on Channel A; a logic 0 indicates that it arrived on Channel B. Bit 7 [1] Channel B Enabled. A logic 1 indicates that Channel B is available for both reception and transmission. Bit 8 [1] Channel A Enabled. A logic 1 indicates that Channel A is available for both reception and transmission. Bit 9 [1] Terminal Flag Enabled. A logic 1 indicates that the Bus Controller has not issued an Inhibit Terminal Flag Mode Code. A logic 0 indicates that the Bus Controller, via the above mode code, is overriding the host system's ability to set the Terminal Flag bit of the status word. Bit 10 [1] Busy. A logic 1 indicates the Busy bit is set. This bit is reset when the System Busy bit in the Control Register is reset. Bit 11 [0] Self-Test. A logic 1 indicates that the chip is in the internal self-test mode. This bit is reset when the self-test is terminated. Bit 12 [0] TA Parity Error. A logic 1 indicates the wrong Terminal Address parity; it causes the biphase inputs to be disabled. TA Parity Error results in the Message Error bit being set to a logic one, and Channels A and B become disabled. Bit 13 [0] Message Error. A logic 1 indicates that a message error has occurred since the last Status Register read. This bit is not reset until the Status Register has been examined. Message error condition must be removed before reading the Status Register to reset the Message Error bit. Bit 14 [0] Valid Message. A logic 1 indicates that a valid message has been received since the last Status Register read. This bit is not reset until the Status Register has been examined. Bit 15 [0] Terminal Active. A logic 1 indicates the device is executing a transmit or receive operation. Same as TERACT output except active high. (Always TERACT; never DSCNCT.) [] - Values in parentheses indicate the initialized values of these bits. STATUS REGISTER (READ ONLY): TERM VAL MESS TAPA SELF- BUSY TFEN CH A CH B CHNL MC/ MCSA MCSA MCSA MCSA MCSA ACTV MESS ERR ERR TEST EN EN A/B SA 4 3 2 1 0 [0] [0] MSB [0] [0] [0] [1] [1] [1] [1] [1] [0] [0] [0] [0] [0] [0] LSB [ ] defines reset state Figure 4b. Status Register RTS-7 1.4 Mode Code and Subaddress The UT1760A RTS provides two modes of illegal subaddress decoding, one meeting MIL-STD-1760A Notices I and II, and the other meeting MIL-STD-1760A Notice III. In addition, the device has automatic internal illegal command decoding for reserved MIL-STD-1553B mode codes. These definitions are extracted from MILSTD-1760A and reviewed in section 1.5 of this document. Upon command word validation and decode, status pins MCSA(4:0) and MC/SA become valid. Status pin MC/SA will indicate whether the data on pins MCSA(4:0) is mode code or subaddress information. Status Register bits 0 through 5 contain the same information as pins MCSA(4:0) and MC/SA. The system designer can use signals MCSA(4:0), MC/SA, BRDCST, RTRT, etc. to illegalize mode codes, subaddresses, and other message formats (broadcast and RT-to-RT) via the Illegal Command (ILLCOM) input to the part. RTS MODE CODE HANDLING PROCEDURE T/R Mode Code Function 0 10100 Selected Transmitter Shutdown 2 0 10101 Override Selected Transmitter Shutdown 2 Synchronize (w/Data) Dynamic Bus Control 2 0 1 10001 00000 1 1 1 1 1 1 1 1 1 1 1 00001 00010 00011 00100 00101 00110 00111 01000 10010 10000 10011 Synchronize 1 Transmit Status Word 3 Initiate Self-Test 1 Transmitter Shutdown Override Transmitter Shutdown Inhibit Terminal Flag Bit Override Inhibit Terminal Flag Reset Remote Terminal 1 Transmit Last Command Word 3 Transmit Vector Word Transmit BIT Word Operation 1. Command word stored 2. MERR pin asserted 3. MERR bit set in Status Register 4. Status word transmitted 1. Command word stored 2. MERR pin asserted 3. MERR bit set in Status Register 4. Status word transmitted 1. Command word stored 2. Data word stored 3. Status word transmitted 1. Command word stored 2. MERR pin asserted 3. MERR bit set in Status Register 4. Status word transmitted 1. Command word stored 2. Status word transmitted 1. Command word stored 2. Status word transmitted 1. Command word stored 2. Status word transmitted 1. Command word stored 2. Alternate bus shutdown 3. Status word transmitted 1. Command word stored 2. Alternate bus enabled 3. Status word transmitted 1. Command word stored 2. Terminal Flag bit set to zero and disabled 3. Status word transmitted 1. Command word stored 2. Terminal Flag bit enabled, but not set to logic one 3. Status word transmitted 1. Command word stored 2. Status word transmitted 1. Status word transmitted 2. Last command word transmitted 1. Command word stored 2. Status word transmitted 3. Data word transmitted 1. Command word stored 2. Status word transmitted 3. Data word transmitted Notes: 1. Further host interaction required for mode code operation. 2. Reserved mode code; A) MERR pin asserted, B) MESS ERR bit set, C) status word transmitted (ME bit set to logic one). 3. Status word not affected. 4. Undefined mode codes are treated as reserved mode codes. RTS-8 1.5 MIL-STD-1760A Subaddress and Mode Code Definitions Table 1. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice I Subaddress Field Binary (Decimal) Message Format Receive Transmit Description 00000 (00) 00001 (01) 00010 (02) 00011 (03) 00100 (04) 00101 (05) 00110 (06) 00111 (07) 01000 (08) 01001 (09) 01010 (10) 01011 (11) 01100 (12) 01101 (13) 01110 (14) 01111 (15) 10000 (16) 10001 (17) 10010 (18) 10011 (19) 10100 (20) 10101 (21) 10110 (22) 10111 (23) 11000 (24) 11001 (25) 11010 (26) 11011 (27) 11100 (28) 11101 (29) 11110 (30) 11111 (31) B.40.1.1.3 Reserved B.40.2.1 2 User Defined Reserved User Defined Reserved User Defined User Defined Reserved User Defined User Defined Reserved User Defined User Defined Reserved Reserved User Defined User Defined User Defined Reserved User Defined Reserved User Defined User Defined User Defined User Defined User Defined Reserved User Defined User Defined User Defined B.40.1.1.3 1 B.40.1.1.3 Store Description User Defined Reserved User Defined Reserved User Defined User Defined Reserved User Defined User Defined Reserved User Defined User Defined Reserved User Defined User Defined User Defined User Defined Reserved User Defined User Defined User Defined User Defined User Defined User Defined User Defined Reserved User Defined User Defined User Defined B.40.1.1.3 Mode Code Indicator Nuclear Weapon Nuclear Weapon Mode Code Indicator Notes: 1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition. 2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition. 3. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted. RTS-9 Table 2. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice II Subaddress Field Binary (Decimal) Message Format Receive Transmit Description 00000 (00) 00001 (01) 00010 (02) 00011 (03) 00100 (04) 00101 (05) 00110 (06) 00111 (07) 01000 (08) 01001 (09) 01010 (10) 01011 (11) 01100 (12) 01101 (13) 01110 (14) 01111 (15) 10000 (16) 10001 (17) 10010 (18) 10011 (19) 10100 (20) 10101 (21) 10110 (22) 10111 (23) 11000 (24) 11001 (25) 11010 (26) 11011 (27) 11100 (28) 11101 (29) 11110 (30) 11111 (31) B.40.1.1.3 Reserved B.40.2.1 2 User Defined Reserved User Defined Reserved User Defined User Defined Reserved User Defined User Defined Reserved User Defined User Defined Reserved Reserved User Defined User Defined User Defined Reserved User Defined Reserved User Defined User Defined User Defined User Defined User Defined Reserved User Defined User Defined User Defined B.40.1.1.3 1 B.40.1.1.3 Store Description User Defined Reserved User Defined Reserved User Defined User Defined Reserved User Defined User Defined Reserved User Defined User Defined Reserved User Defined User Defined User Defined User Defined Reserved User Defined User Defined User Defined User Defined User Defined User Defined User Defined Reserved User Defined User Defined User Defined B.40.1.1.3 Mode Code Indicator Nuclear Weapon Nuclear Weapon Mode Code Indicator Notes: 1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition. 2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition. 3. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted. RTS-10 Table 3. Subaddress and Mode Code Definitions Per MIL-STD-1760A Notice III Subaddress Field Binary (Decimal) Message Format Receive Transmit Description 00000 (00) 00001 (01) 00010 (02) 00011 (03) 00100 (04) 00101 (05) 00110 (06) 00111 (07) 01000 (08) 01001 (09) 01010 (10) 01011 (11) 01100 (12) 01101 (13) 01110 (14) 01111 (15) 10000 (16) 10001 (17) 10010 (18) 10011 (19) 10100 (20) 10101 (21) 10110 (22) 10111 (23) 11000 (24) 11001 (25) 11010 (26) 11011 (27) 11100 (28) 11101 (29) 11110 (30) 11111 (31) B.40.1.1.3 Reserved B.40.2.1 2 User Defined User Defined User Defined User Defined User Defined User Defined Reserved User Defined User Defined B.40.2.2.1 3 User Defined User Defined B.40.1.1.5.8 4 User Defined User Defined User Defined User Defined B.40.2.2.4 5 User Defined User Defined User Defined User Defined User Defined User Defined User Defined B.40.2.2.4 User Defined User Defined User Defined B.40.1.1.3 1 B.40.1.1.3 Store Description User Defined User Defined User Defined User Defined User Defined User Defined Reserved User Defined User Defined B.40.2.2.1 User Defined User Defined B.40.1.5.8 User Defined User Defined User Defined User Defined B.40.2.2.5 6 User Defined User Defined User Defined User Defined User Defined User Defined User Defined B.40.2.2.5 User Defined User Defined User Defined B.40.1.1.3 Mode Code Indicator Test Only Mission Store Control/Monitor Mass Data Transfer Nuclear Weapon Nuclear Weapon Mode Code Indicator Notes: 1. Refer to section B.40.1.1.3 of the MIL-STD-1760A specification for definition. 2. Refer to section B.40.2.1 of the MIL-STD-1760A specification for definition. 3. Refer to section B.40.2.2.1 of the MIL-STD-1760A specification for definition. 4. Refer to section B.40.1.1.5.8 of the MIL-STD-1760A specification for definition. 5. Refer to section B.40.2.2.4 of the MIL-STD-1760A specification for definition. 6. Refer to section B.40.2.2.5 of the MIL-STD-1760A specification for definition. 7. Reserved subaddresses illegalized; Message Error bit and pin set; SW transmitted. RTS-11 1.6 Terminal Address The Terminal Address of the RTS is programmed via five input pins: RTA(4:0) and RTPTY. Asserting MRST latches the RTS's Terminal Address from pins RTA(4:0) and parity bit RTPTY. The address and parity cannot change until the next assertion of the MRST. The parity of the Terminal Address is odd; input pin RTPTY is set to a logic state to satisfy this requirement. A logic 1 on Status Register bit 12 indicates incorrect Terminal Address parity. An example follows: RTA(4:0) = 05 (hex) = 00101 RTPTY = 1 (hex) = 1 Sum of 1's = 3 (odd), Status Register bit 12 = 0 RTA(4:0) = 04 (hex) = 00100 RTPTY = 0 (hex) = 0 Sum of 1's = 1 (odd), Status Register bit 12 = 0 RTA(4:0) = 04 (hex) = 00100 RTPTY = 1 (hex) = 1 Sum of 1's = 2 (even), Status Register bit 12 = 1 1.8 Power-up and Master Reset After power-up, reset initializes the part with its biphase ports enabled, latches the Terminal Address, selects Notice III subaddress decoding, and turns on the busy option. The device is ready to accept commands from the MIL-STD1553B bus. The busy flag is asserted while the host is loading the message pointers and messages. After this task is completed, the host removes the busy condition via a Control Register write to the RTS. On power-up if the terminal address parity (odd) is incorrect, the biphase inputs are disabled and the message error pin (MERR) is asserted. This condition can also be monitored via bit 12 of the Status Register. The MERR pin is negated on reception of first valid command. 1.9 Encoder and Decoder The RTS interfaces directly to a bus transmitter/ receiver via the RTS Manchester II encoder/decoder. The UT1760A RTS receives the command word from the MIL-STD1553B bus and processes it either by the primary or secondary decoder. Each decoder checks for the proper sync pulse and Manchester waveform, edge skew, correct number of bits, and parity. If the command is a receive command, the RTS processes each incoming data word for correct format and checks the control logic for correct word count and contiguous data. If an invalid message error is detected, the message error pin is asserted, the RTS ceases processing the remainder (if any) of the message, and it then suppresses status word transmission. Upon command validation recognition, the external status outputs are enabled. Reception of illegal commands does not suppress status word transmission. The RTS automatically compares the transmitted word (encoder word) to the reflected decoder word by way of the continuous loop-back feature. If the encoder word and reflected word do not match, the transmitter error pin (TXERR) is asserted. In addition to the loop-back compare test, a timer precludes a transmission greater than 760s by the assertion of Fail-safe Timer (TIMERON). This timer is reset upon receipt of another command. (RT-to-RT transfer time-out = 57s). The RTS checks the Terminal Address and parity on Master Reset. The state of the DSCNCT signal indicates the mated status of the store. When all six Terminal Address pins (RTA(4:0), RTPTY) go to a logic one, the DSCNCT pin is asserted. To enable the disconnect function (DSCNCT pin) bit 11 of the Control Register is set to a logic one. With broadcast disabled, RTA (4:0) = 11111 operates as a normal RT address. 1.7 Internal Self-Test Setting bit 6 of the Control Register to a logic one enables the internal self-test. Disable Channels A and B at this time to prevent bus activity during self-test by setting bits 0 and 1 of the Control Register to a logic zero. Normal operation is inhibited when internal self-test is enabled. The self-test capability of the RTS is based on the fact that the MIL-STD1553B status word sync pulse is identical to the command word sync pulse. Thus, if the status word from the encoder is fed back to the decoder, the RTS will recognize the incoming status word as a command word and thus cause the RTS to transmit another status word. After the host invokes self-test, the RTS self-test logic forces a status word transmission even though the RTS has not received a valid command. The status word is sent to decoder A or B depending on the channel the host selected for self-test. The self-test is controlled by the host periodically changing the bit patterns in the status word being transmitted. Writing to the Control Register bits 2, 3, 4, 7, 8, and 10 changes the status word. Monitor the self-test by sampling either the Status Register or the external status pins (i.e., Command Strobe (COMSTR), Transmit/Receive (T/R)). For more detailed explanation of internal self-test, consult UTMC publication RTR/RTS Internal Self-Test Routine. 1.10 RT-RT Transfer Compare The RT-to-RT Terminal Address compare logic makes sure that the incoming status word's Terminal Address matches the Terminal Address of the transmitting RT specified in the command word. An incorrect match results in setting the message error bit and suppressing transmission of the status word. RTS-12 1.11 Illegal Command Decoding The host has the option of asserting the ILLCOM pin to illegalize a received command word. On receipt of an illegal command, the RTS sets the Message Error bit in the status word, sets the message error output, and sets the message error latch in the Status Register. The following RTS outputs may be used to externally decode an illegal command, Mode Code or Subaddress indicator (MC/SA), Mode Code or Subaddress bus MCSA(4:0), Command Strobe (COMSTR), Broadcast (BRDCST), and Remote Terminal to Remote Terminal transfer (RTRT) (see figure 21 on page 34.) To illegalize a transmit command, the ILLCOM pin must be asserted within 3.3s after VALMSG goes to a logic 1 if the RTS is to respond with the Message Error bit of the status word at a logic 1. If the illegal command is mode code 2, 4, 5, 6, 7, or 18, the ILLCOM pin must be asserted within 664ns after Command Strobe (COMSTR) transitions to logic 0. Asserting the ILLCOM pin within the 664ns inhibits the mode code function. For mode code illegalization, assert the ILLCOM pin until the VALMSG signal is asserted. For an illegal receive command, the ILLCOM pin must be asserted within 18.2s after the COMSTR transitions to a logic 0 in order to suppress data words from being stored. In addition, the ILLCOM pin must be at a logic 1 throughout the reception of the message until VALMSG is asserted. This does not apply to illegal transmit commands since the status word is transmitted first. The above timing conditions also apply when the host externally decodes an illegal broadcast command. The host must remove the illegal command condition so that the next command is not falsely decoded as illegal. 2.0 MEMORY MAP EXAMPLE Figures 5 and 6 illustrate the UT1760A RTS buffering three receive command messages to Subaddress 4. The receive message pointer for Subaddress 4 is located at 03C4 (hex) in the 1K x 16 RAM. The 16-bit contents of location 03C4 (hex) point to the memory location where the first receive message is stored. The Address Field defined as bits 0 through 9 of address 03C4 (hex) contain address information. The Index Field defined as bits 10 through 15 of address 03C4 (hex) contain the message buffer index (i.e., number of messages buffered). Figure 5 demonstrates the updating of the message pointer as each message is received and stored. The memory storage of these three messages is shown in figure 6. After receiving the third message for Subaddress 4 (i.e., Index Field equals zero) the Address Field of the message pointer is not incremented. If the host does not update the receive message pointer for Subaddress 4 before the next receive command for Subaddress 4 is accepted, the third message will be overwritten. Figures 7 and 8 show an example of multiple message retrieval from Subaddress 16 upon reception of a MIL-STD1553B transmit command. The message pointer for transmit Subaddress 16 is located at 03F0 (hex) in the 1K x 16 RAM. The 16-bit contents of location 03F0 (hex) point to the memory location where the first message data words are stored. Figure 7 demonstrates the updating of the message pointer as each message is received and stored. The data memory for these three messages is shown in figure 8. RTS-13 Example: Remote terminal will receive and buffer three MIL-STD-1553 receive commands of various word lengths to Subaddress 4. MIL-STD-1553 Bus Activity: CMD WORD #1 DW0 DW1 DW2 DW3 CMD WORD #2 DW0 DW1 CMD WORD #3 DW0 DW1 DW2 DW3 SA = 4 T/R = 0 WC = 4 SA = 4 T/R = 0 WC = 2 03C4 (hex) Receive Subaddress 4; data pointer at 03C4 (hex). (Initial condition) After message #1, 4 data words plus command word. After message #2, 2 data words plus command word. After message #3, 4 data words plus command word. SA = 4 T/R = 0 WC = 4 INDEX = 0000 10 0840 (hex) ADDRESS = 00 0100 0000 0445 (hex) INDEX = 0000 01 ADDRESS = 00 0100 0101 INDEX = 0000 00 ADDRESS = 00 0100 1000 INDEX = 0000 00 ADDRESS = 00 0100 1000 03C4 (hex) 03C4 (hex) 0048 (hex) 03C4 (hex) 0048 (hex) Figure 5. RTS Message Handling 03C4 (hex) 0840 (hex) COMMAND WORD #1 DATA WORD 0 DATA WORD 1 DATA WORD 2 DATA WORD 3 040 (hex) 041 (hex) 042 (hex) 043 (hex) 044 (hex) 045 (hex) 046 (hex) 047 (hex) 048 (hex) 049 (hex) 04A (hex) 04B (hex) 04C (hex) 03C4 (hex) 0445 (hex) COMMAND WORD #2 DATA WORD 0 DATA WORD 1 03C4 (hex) 0048 (hex) COMMAND WORD #3 DATA WORD 0 DATA WORD 1 DATA WORD 2 03C4 (hex) 0048 (hex) DATA WORD 3 Figure 6. Memory Storage Subaddress 4 RTS-14 Example: Remote terminal will transmit and buffer three MIL-STD-1553 transmit commands of various word lengths to Subaddress 16. MIL-STD-1553 Bus Activity: CMD WORD #1 SW DW0 DW1 DW2 DW3 SA = 16 CMD WORD #2 SW SW0 DW1 T/R = 1 WC = 4 SA = 16 CMD WORD #3 SW DW0 DW1 DW2 DW3 T/R = 1 WC = 2 SA = 16 T/R = 1 WC = 4 Transmit Subaddress 16; data pointer at 03F0 (hex). (Initial condition) 03F0 (hex) 0830 (hex) INDEX = 0000 10 ADDRESS = 00 0011 0000 INDEX = 0000 01 ADDRESS = 00 0011 0100 INDEX = 0000 00 ADDRESS = 00 0011 0110 INDEX = 0000 00 ADDRESS = 00 0011 0110 After message #1, 4 data words. After message #2, 2 data words. After message #3, 4 data words. 03F0 (hex) 0434 (hex) 03F0 (hex) 0036 (hex) 03F0 (hex) 0036 (hex) Figure 7. RTS Message Handling 03F0(hex) 0830 (hex) DATA WORD 0 DATA WORD 1 DATA WORD 2 DATA WORD 3 DATA WORD 0 DATA WORD 1 030 (hex) 031 (hex) 032 (hex) 033 (hex) 034 (hex) 035 (hex) 036 (hex) 037 (hex) 038 (hex) 039 (hex) 03F0 (hex) 0434 (hex) 03F0 (hex) 0036 (hex) DATA WORD 0 DATA WORD 1 DATA WORD 2 03F0 (hex) 0036 (hex) 034 (hex) DATA WORD 3 Note: Example is valid only if message structure is known in advance. Figure 8. Memory Storage Subaddress 16 RTS-15 3.0 PIN IDENTIFICATION AND DESCRIPTION BIPHASE OUT TAZ TAO TBZ TBO BIPHASE IN RAZ RAO RBZ RBO RTA0 RTA1 RTA2 RTA3 RTA4 RTPTY MCSA0 MCSA1 MCSA2 MCSA3 MCSA4 A10 B10 A9 B9 L7 K8 L6 K7 L5 K5 L4 K4 L3 K6 B2 A2 A3 B3 A4 A5 A6 B5 B6 B8 B1 A7 B4 B7 L8 C2 K2 K1 J1 L9 K9 J2 H1 H2 G1 G2 F1 E2 D1 D2 C1 L10 K10 K11 J10 J11 H10 H11 G10 F11 E10 E11 D10 D11 C10 C11 B11 F10 E1 F2 G11 L2 A8 K3 ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 VDD VDD VSS VSS 12MHZ 2MHZ MRST POWER GROUND ADDRESS BUS ADDR(9:0) TERMINAL ADDRESS DATA BUS DATA(15:0) MODE/CODE SUBADDRESS UT1760A RTS STATUS SIGNALS MERR DSCNCT/TERACT TXERR TIMERON COMSTR MC/SA BRDCST T/R RTRT VALMSG RBUSY CONTROL SIGNALS CS RD/WR CTRL OE ILLCOM CLOCK RESET Figure 9. UT1760A RTS Pin Description RTS-16 Legend for TYPE and ACTIVE Fields: TI = TTL input TUI = TTL input (pull-up) TDI = TTL input (pull-down) TO = TTL output DATA BUS NAME PIN NUMBER (PGA) B11 TYPE ACTIVE TTO = Three-state TTL output TTB = Three-state TTL bidirectional AL = Active low AH = Active high [] - Value in parentheses indicates initial state of these pins. DESCRIPTION DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 C11 C10 D11 D10 E11 E10 F11 G10 H11 H10 J11 J10 K11 K10 L10 TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB TTB ----------------- Bit 15 (MSB) of the bidirectional Data bus. Bit 14 of the bidirectional Data bus. Bit 13 of the bidirectional Data bus. Bit 12 of the bidirectional Data bus. Bit 11 of the bidirectional Data bus. Bit 10 of the bidirectional Data bus. Bit 9 of the bidirectional Data bus. Bit 8 of the bidirectional Data bus. Bit 7 of the bidirectional Data bus. Bit 6 of the bidirectional Data bus. Bit 5 of the bidirectional Data bus. Bit 4 of the bidirectional Data bus. Bit 3 of the bidirectional Data bus. Bit 2 of the bidirectional Data bus. Bit 1 of the bidirectional Data bus. Bit 0 (LSB) of the bidirectional Data bus. ADDRESS BUS NAME PIN NUMBER (PGA) C1 TYPE ACTIVE DESCRIPTION ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 D2 D1 E2 F1 G2 G1 H2 H1 J2 TI TI TI TI TI TI TI TI TI TI ----------- Bit 9 (MSB) of the Address bus. Bit 8 of the Address bus. Bit 7 of the Address bus. Bit 6 of the Address bus. Bit 5 of the Address bus. Bit 4 of the Address bus. Bit 3 of the Address bus. Bit 2 of the Address bus. Bit 1 of the Address bus. Bit 0 (LSB) of the Address bus. RTS-17 CONTROL INPUTS NAME PIN NUMBER (PGA) K2 TYPE ACTIVE DESCRIPTION CS TI AL RD/WR K1 TI -- CTRL J1 TI AL OE L9 TI AL Chip Select. The host processor uses the CS signal for RTS Status Register reads, Control Register writes, or host access to the RTS internal RAM. Read/Write. The host processor uses a high level on this input in conjunction with CS to read the RTS Status Register or the RTS internal RAM. A low level on this input is used in conjunction with CS to write to the RTS Control Register or the RTS internal RAM. Control. The host processor uses the active low CTRL input signal in conjunction with CS and RD/WR to access the RTS registers. A high level on this input means access is to RTS internal RAM only. Output Enable. The active low OE signal is used to control the direction of data flow from the RTS. For OE = 1, the RTS Data bus is three-state; for OE = 0, the RTS Data bus is active. Illegal Command. The host processor uses the ILLCOM input to inform the RTS that the present command is illegal. ILLCOM K9 TDI AH RTS-18 STATUS OUTPUTS NAME PIN NUMBER (PGA) A5 TYPE ACTIVE DESCRIPTION MERR [0] TO AH TXERR [0] B5 TO AH TIMERON [1] B6 TO AL COMSTR [1] BRDCST [1] RTRT [0] DSCNCT or TERACT [X] B8 A7 B7 TO TO TO AL AL AH A6 TO -- VALMSG [0] L8 TO AH RBUSY [0] C2 TO AH T/R [0] B4 TO -- Message Error. The active high MERR output signals that the Message Error bit in the Status Register has been set due to receipt of an illegal command, or an error during message sequence. MERR will reset to logic zero on the receipt of the next valid command. Transmission Error. The active high TXERR output is asserted when the RTS detects an error in the reflected word versus the transmitted word, using the continuous loop-back compare feature. Reset on next COMSTR assertion. Fail-safe Timer. The TIMERON output pulses low for 760s when the RTS begins transmitting (i.e., rising edge of VALMSG) to provide a fail-safe timer meeting the requirements of MIL-STD-1553B. This pulse is reset when COMSTR goes low or during a Master Reset. Command Strobe. COMSTR is an active low output of 500ns duration identifying receipt of a valid command. Broadcast. BRDCST is an active low output that identifies receipt of a valid broadcast command. Remote Terminal to Remote Terminal. RTRT is an active high output indicating that the RTS is processing a remote terminal to remote terminal command. Disconnect or Terminal Active. Bit 11 of the Control Register selects the mode of this dual-function pin. In the "Disconnect" mode (bit 11 = 1), the active high DSCNCT output is asserted when all six Terminal Address pins (RTA0 - RTA4, RTPTY) go high, indicating a disconnect condition. In the "Terminal Active" mode (bit 11 = 0), the active low TERACT output is asserted at the beginning of the RTS access to internal RAM for a given command and negated after the last access for that command. Valid Message. VALMSG is an active high output indicating a valid message (including Broadcast) has been received. VALMSG goes high prior to transmitting the 1553 status word and is reset upon receipt of the next command. RTS Busy. RBUSY is asserted high while the RTS is accessing its own internal RAM either to read or update the pointers or to store or retrieve data words. RBUSY becomes active either 2.7s or 5.7s before RTS requires RAM access. This timing is controlled by Control Register bit 12 (see section 1.3). Transmit/Receive. A high level on this pin indicates a transmit command message transfer is being or was processed, while a low level indicates a receive command message transfer is being or was processed. RTS-19 MODE CODE/SUBADDRESS OUTPUTS NAME PIN NUMBER (PGA) B1 TYPE ACTIVE DESCRIPTION MC/SA [0] TO -- MCSA0 [0] B2 TO -- MCSA1 [0] MCSA2 [0] MCSA3 [0] MCSA4 [0] A2 A3 B3 A4 TO TO TO TO ----- Mode Code/Subaddress Indicator. If MC/SA is low, it indicates that the most recent command word is a mode code command. If MC/SA is high, it indicates that the most recent command word is for a subaddress. This output indicates whether the mode code/subaddress ouputs (i.e., MCSA(4:0)) contain mode code or subaddress information. Mode Code/Subaddress Output 0. If MC/SA is low, this pin represents the least significant bit of the most recent command word (the LSB of the mode code). If MC/SA is high, this pin represents the LSB of the subaddress. Mode Code/Subaddress Output 1. Mode Code/Subaddress Output 2. Mode Code/Subaddress Output 3. Mode Code/Subaddress Output 4. If MC/SA is low, this pin represents the most significant bit of the mode code. If MC/ SA is high, this pin represents the MSB of the subaddress. REMOTE TERMINAL ADDRESS INPUTS NAME PIN NUMBER (PGA) L3 TYPE ACTIVE DESCRIPTION RTA4 RTA3 RTA2 RTA1 RTA0 RTPTY K4 L4 K5 L5 K6 TUI TUI TUI TUI TUI TUI ------- Remote Terminal Address bit 4 (MSB). Remote Terminal Address bit 3. Remote Terminal Address bit 2. Remote Terminal Address bit 1. Remote Terminal Address bit 0 (LSB). Remote Terminal Address Parity. This input must provide odd parity for the Remote Terminal Address. RTS-20 BIPHASE INPUTS 1 NAME PIN NUMBER (PGA) L7 TYPE ACTIVE DESCRIPTION RAZ RAO RBZ RBO TI TI TI TI ----- K8 L6 K7 Receiver - Channel A, Zero Input. Idle low Manchester input form the 1553 bus receiver. Receiver - Channel A, One Input. This input is the complement of RAZ. Receiver - Channel B, Zero Input. Idle low Manchester input from the 1553 bus receiver. Receiver - Channel B, One Input. This input is the complement of RBZ. Note: 1. For uniphase operation, tie RAZ (or RBZ) to VDD and apply true uniphase input signal to RAO (or RBO). BIPHASE OUTPUTS NAME PIN NUMBER (PGA) A10 TYPE ACTIVE DESCRIPTION TAZ [0] TAO [0] TBZ [0] TBO [0] TO -- B10 A9 TO TO --- Transmitter - Channel A, Zero Output. This Manchester encoded data output is connected to the 1553 bus transmitter input. The output is idle low. Transmitter - Channel A, One Output. This output is the complement of TAZ. The output is idle low. Transmitter - Channel B, Zero Output. This Manchester encoded data output is connected to the 1553 bus transmitter input. The output is idle low. Transmitter - Channel B, One Output. This output is the complement of TBZ. The output is idle low. B9 TO -- MASTER RESET AND CLOCK NAME PIN NUMBER (PGA) K3 TYPE ACTIVE DESCRIPTION MRST TUI AL 12MHz L2 TI -- 2MHz A8 TO -- Master Reset. Initializes all internal functions of the RTS. MRST must be asserted 500ns before normal RTS operation (500ns minimum). Does not reset RAM. 12 MHz Input Clock. This is the RTS system clock that requires an accuracy greater than 0.01% with a duty cycle of 50% 10%. 2MHz Clock Output. This is a 2MHz clock output generated by the 12MHz input clock. This clock is stopped when MRST is low. RTS-21 POWER AND GROUND NAME PIN NUMBER (PGA) F10 E1 TYPE ACTIVE DESCRIPTION VDD VSS F2 G11 PWR PWR GND GND ----- +5 VDC Power. Power supply must be +5 VDC 10%. Reference ground. Zero VDC logic ground. 4.0 OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS* (referenced to VSS) SYMBOL VDD PARAMETER DC supply voltage Voltage on any pin DC input current Storage temperature Maximum power dissipation 1 Maximum junction temperature Thermal resistance, junction-to-case LIMITS -0.3 to +7.0 -0.3 to VDD+0.3 10 -65 to +150 300 +175 20 UNIT V VIO II TSTG PD TJ JC Note: 1. Does not reflect the added PD due to an output short-circuited. * Stressesoutsidethelistedabsolutemaximumratings may cause permanent damage to the device.Thisisa stressrating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. V mA C mW C C/W RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC FO PARAMETER DC supply voltage DC input voltage Temperature range Operating frequency LIMITS 4.5 to 5.5 0 to VDD -55 to +125 12 .01% UNIT V V C MHz RTS-22 5.0 DC ELECTRICAL CHARACTERISTICS VDD = 5.0V 10%; -55C < TC <+125C) SYMBOL VIL PARAMETER Low-level input voltage High-level input voltage Input leakage current TTL inputs Inputs with pull-down resistors Inputs with pull-up resistors Low-level output voltage High-level output voltage Three-state output leakage current CONDITION MINIMUM MAXIMUM 0.8 UNIT V VIH IIN 2.0 VIN = VDD or VSS VIN = VDD VIN = VSS IOL = 3.2A IOH = -400A VO = VDD or VSS VDD = 5.5V, VO = VDD VDD = 5.5V, VO = 0V = 1MHz @ 0V = 1MHz @ 0V = 1MHz @ 0V = 12MHz, CL = 50pF Note 5 -1 110 -2000 2.4 -10 1 2000 -110 0.4 +10 90 -90 V A A A V V A mA mA VOL VOH IOZ IOS Short-circuit output current 1, 2 CIN Input capacitance 3 10 pF COUT Output capacitance 3 15 pF CIO Bidirect I/O capacitance 3 20 pF IDD Average operating current 1, 4 50 mA QIDD Quiescent current 1.5 mA Notes: 1. Supplied as a design limit but not guaranteed or tested. 2. Not more than one output may be shorted at a time for a maximum duration of one second. 3. Measured only for initial qualification, and after process or design changes that could affect input/output capacitance. 4. Includes current through input pull-ups. Instantaneous surge currents on the order of 1 ampere can occur during output switching. Voltage supply should be adequately sized and decoupled to handle a large surge current. 5. All inputs with internal pull-ups or pull-downs should be left open circuit. All other inputs tied high or low. BIT TIMES COMMAND WORD SYNC DATA WORD SYNC STATUS WORD SYNC 5 REMOTE TERMINAL ADDRESS 123 45678 5 9 1 10 11 12 13 14 5 15 16 17 18 19 5 20 1 P 1 P REMOTE TERMINAL T/R SUBADDRESS/MODE DATA WORD COUNT/ MODE CODE ADDRESS CODE 16 DATA 1 MESSAGE ERROR 1 INSTRUMENTATION 1 SERVICE REQUEST RESERVED 1 BROADCAST COMMAND RECEIVED 1 BUSY 1 SUBSYSTEM FLAG 1 DYNAMIC BUS CONTROL ACCEPTANCE 1 TERMINAL FLAG 1 PARITY Figure 10. MIL-STD-1553B Word Formats RTS-23 6.0 AC ELECTRICAL CHARACTERISTICS (Over recommended operating conditions) VIH MIN 1 INPUT V MAX IL ta IN-PHASE 2 OUTPUT OUT-OF-PHASE OUTPUT BUS tf tg th tc 2 VIH MIN VIL MAX VOH MIN VOL MAX VOH MIN VOL MAX VOH MIN VOL MAX 1 tb 2 td 2 te SYMBOL ta tb tc td te tf tg th INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT PARAMETER to response to response to response to response to data valid to high Z to high Z to data valid Notes: 1. Timing measurements made at (VIH MIN + VIL MAX)/2. 2. Timing measurements made at (VOL MAX + VOH MIN)/2. 3. Based on 50pf load. 4. Unless otherwise noted, all AC electrical characteristics are guaranteed by design or characterization. Figure 11a. Typical Timing Measurements 5V IREF (source) 90% VREF D 50pF 10% 0V 10% 3V 90% IREF (sink) < 2ns Input Pulses < 2ns Note: 50pF including scope probe and test socket Figure 11b. AC Test Loads and Input Waveforms RTS-24 12MHz CS t12a CTRL t12b RD/WR t12c ADDR(9:0) t12d DATA(15:0) t12e OE t12i t12j t12f t12k t12g t12l DATA VALID t1h t12m Figure 12. Microprocessor RAM Read SYMBOL PARAMETER 1 MIN MAX UNITS 10 -ns t12a CTRL set up wrt CS 10 -ns t12b RD/WR set up wrt CS 10 -ns t12c ADDR(9:0) Valid to CS (Address Set up) -155 ns t12d CS to DATA(15:0) Valid -65 ns t12e OE to DATA(15:0) Don't Care (Active) 0 -ns t12f CS to CTRL Don't Care 0 -ns t12g CS to ADDR(9:0) Don't Care -40 ns t12h OE to DATA(15:0) High Impedance 2 220 5500 ns t12i CS to CS 85 -ns t12j CS to CS 0 -ns t12k CS to RD/WR Don't Care 25 -ns t12l CS to DATA(15:0) Invalid 3 65 -ns t12m OE to OE Notes: 1. "wrt" defined as "with respect to." 2. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7s RBUSY option. For the 2.7s RBUSY option, the maximum CS low time is 2500ns. 3. Assumes OE is asserted. RTS-25 12MHz CS t13a CTRL t13b RD/WR t13i t13j t13k t13f t13c ADDR(9:0) t13g t13d DATA(15:0) VALID DATA t13h OE t13e Figure 13. Microprocessor RAM Write SYMBOL t13a t13b t13c t13d t13e t13f t13g t13h t13i t13j t13k PARAMETER CTRL set up wrt CS RD/WR set up wrt CS ADDR(9:0) Valid to CS (Address set up) CS to DATA(15:0) Valid CS(DATA set up) OE to DATA(15:0) High Impedance CS to RD/WR Don't Care CS to ADDR(9:0) Don't Care CS to DATA(15:0) Don't Care (Hold-time) CS to CS 1 CS to CS CS to CTRL Don't Care MIN 10 10 10 0 40 0 0 20 180 85 0 MAX --------5500 --- UNITS ns ns ns ns ns ns ns ns ns ns ns Note: 1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7s RBUSY option. For the 2.7s RBUSY option, the maximum CS low time is 2500ns. RTS-26 12MHz CS t14c t14a CTRL t14e t14b RD/WR t14f DATA(15:0) t14h VALID DATA t14d OE t14g Figure 14. Control Register Write SYMBOL t14a t14b t14c t14d t14e t14f t14g t14h PARAMETER CTRL set up wrt CS RD/WR set up wrt CS CS to CS 1 CS to DATA(15:0) Don't Care (Hold-time) CS to CTRL Don't Care CS to RD/WR Don't Care OE to Data(15:0) High Impedance DATA (15:0) Valid to CS (DATA set up) MIN 0 0 50 0 0 0 40 0 MAX --5500 ------ UNITS ns ns ns ns ns ns ns ns Note: 1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7s RBUSY option. For the 2.7s RBUSY option, the maximum CS low time is 2500ns. RTS-27 12MHz CS t15b t15a CTRL t15e t15c RD/WR t15d DATA(15:0) VALID DATA t15f t15j t15g OE t15h t15i Figure 15. Status Register Read SYMBOL t15a t15b t15c t15d t15e t15f t15g t15h t15i t15j PARAMETER CTRL set up wrt CS CS to CS1 RD/WR set up wrt CS CS to DATA(15:0) Valid CS to CTRL Don't Care CS to RD/WR Don't Care OE to DATA(15:0) Don't Care (Active) OE to DATA(15:0) High Impedance OE to OE CS to DATA(15:0) Don't Care (Active) MIN 0 65 0 -5 5 --65 25 MAX -5500 -65 --65 40 --- UNITS ns ns ns ns ns ns ns ns ns ns Note: 1. The maximum amount of time that CS can be held low is 5500ns if the user has selected the 5.7s RBUSY option. For the 2.7s RBUSY option, the maximum CS low time is 2500ns. RTS-28 VALMSG t16a TIMERON t16c A/B BIPHASE OUTPUT ZERO t16b COMSTR t16d ILLCOM t16g t16e t16f Figure 16. RT Fail-Safe Timer Signal Relationships SYMBOL PARAMETER MIN 0 1.2 727.3 ----500 MAX 35 -727.4 25 3.3 664 18.2 -- UNITS ns s s ns s ns s ns t16a VALMSG before TIMERON t16b TIMERON before first BIPHASE OUT O t16c TIMERON low pulse width (time-out) t16d COMSTR to TIMERON t16e VALMSG to ILLCOM t16f COMSTR to ILLCOM 1 t16f COMSTR to ILLCOM 2 t16g ILLCOM to ILLCOM 3 Notes: 1. Mode code 2, 4, 5, 6, 7, or 18 received. 2. To suppress data word storage. 3. For transmit command illegalization. RTS-29 12MHz CS BIPHASE IN MC/SA and MCSA(4:0) COMMAND WORD P 1 t17a t17b t17c t17l COMSTR t17d t17e BRDCST t17f t17g T/R t17h t17i VALMSG t17j t17k MERR Note: 1. Measured from the mid-bit parity crossing. Figure 17. Status Output Timing SYMBOL 4 PARAMETER MIN 0 2.1 0 3.2 0 2.6 0 2.2 0 6.2 0 485 MAX 14 2.8 17 3.7 32 3.2 57 2.7 32 6.7 37 500 UNITS ns s ns s ns s ns s ns s ns ns t17a 12Mhz to MC/SA Valid t17b Command Word to MC/SA Valid3 4 t17c 12MHz to COMSTR t17d Command Word to COMSTR3 4 t17e 12MHz to BRDCST t17f Command Word to BRDCST3 4 t17g 12MHz to T/R Valid t17h Command Word toT/R Valid3 4 t17i 12MHz to VALMSG t17j Command Word toVALMSG 1,2,3 t17k 4 12MHz to MERR t17l COMSTR TO COMSTR Notes: 1. Receive last data word to Valid Message active (VALMSG). 2. Transmit command word to Valid Message active (VALMSG). 3. Command word measured from mid-bit crossing. 4. Guaranteed by test. RTS-30 12MHz CS COMMAND WORD P BIPHASE IN RBUSY t18a t18i t18b t18c t18h TERACT t18d t18e RTRT t18f t18g MRST Note: 1. Measured from mid-bit parity crossing. Figure 18. Status Output Timing SYMBOL t18a t18b t18c2 t18d t18e 2 t18f t18g t18h t18i PARAMETER 12MHz to RBUSY Command Word toRBUSY 3 12MHz to TERACT Command Word to TERACT 1,3 12MHz to RTRT Command Word to RTRT 3 MRST to MRST RBUSY to RBUSY (2.7s) (5.7s) RBUSY to RBUSY (2.7s) (5.7s) MIN -3.2 0 3.1 0 21.0 500 --3.10 240 MAX 37 3.8 37 3.7 32 22 -5.5 8.5 --UNITS ns s ns s ns s ns s s s ns Notes: 1. TERACT enabled via Control Register. 2. Guaranteed by test. 3. Command word measured from mid-bit crossing RTS-31 BIPHASE IN CS COMMAND WORD DS DATA WORD P DS DATA WORD P COMSTR T/R RBUSY TERACT BIPHASE OUT VALMSG 1 2 3 SS STATUS WORD P Notes: 1. Burst of 5 DMAs: read command pointer, store command word, update command pointer, read data word pointer, store command word. 2. Burst of 1 DMA: store data word. 3. Burst of 2 DMAs: store data word, update data word pointer. 4. Approximately 560ns per DMA access. Figure 19a. Receive Command with Two Data Words BIPHASE IN CS COMMAND WORD P COMSTR T/R RBUSY 1 2 3 TERACT BIPHASE OUT SS STATUS WORD P DS DATA WORD P DS DATA WORD P VALMSG CS = Command sync SS = Status sync DS = Data sync P = Parity Notes: 1. Burst of 4 DMAs: read command pointer, store command word, update command pointer, read data word pointer. 2. Burst of 1 DMA: read data word. 3. Burst of 2 DMAs: read data word, update data word pointer. 4. Approximately 560ns per DMA access. Figure 19b. Transmit Command with Two Data Words RTS-32 ADDR(9:0) DATA(15:0) UT1760A RTS CONTROL HOST SUBSYSTEM UT63M125 1553 TRANSCEIVER 1553 BUS A 1553 BUS B Figure 20a. RTS General System Diagram (Idle low interface) RAO RAZ CHANNEL A TAO TAZ RTS RBO RBZ CHANNEL B TBO TBZ TXINHB TXINHB RXOUT RXOUT CHANNEL A TXIN TXIN UTMC 63M125 RXOUT RXOUT CHANNEL B TXIN TXIN TIMERON Figure 20b. RTS Transceiver Interface Diagram RTS-33 MC/SA MCSA0 MCSA1 MCSA2 MCSA3 RTS MCSA4 COMSTR BRDCST T/R RTRT ILLCOM ILLEGAL COMMAND DECODER Figure 21. Mode Code/Subaddress Illegalization Circuit 7.0 PACKAGE OUTLINE DRAWING RTS-34 L K J H G F L2 K1 J1 H1 G1 F1 E1 D1 C1 B1 K2 J2 H2 G2 L3 K3 L4 K4 L5 K5 L6 K6 L7 K7 L8 K8 L9 K9 L10 K10 J10 H10 G10 K11 J11 H11 G11 F11 E11 D11 C11 B11 F2 E2 D2 C2 B2 A2 B3 A3 3 B4 A4 4 C1 C2 C10 C11 D1 D2 D10 D11 E1 E2 E10 E11 F1 B5 A5 5 ADDR9 RBUSY DATA13 DATA14 ADDR7 ADDR8 DATA11 DATA12 VDD ADDR6 DATA9 DATA10 ADDR5 B6 A6 6 B7 A7 7 G1 G2 G10 G11 H1 H2 H10 H11 J1 J2 B8 A8 8 ADDR3 ADDR4 DATA7 VSS ADDR1 ADDR2 DATA5 DATA6 CTRL ADDR0 B9 A9 9 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 L2 L3 L4 L5 L6 L7 L8 F10 E10 D10 C10 B10 A10 10 E D C B A 1 A2 A3 A4 A5 A6 2 11 MCSA1 MCSA2 MCSA4 MERR TERACT or DSCNCT A7 BRDCST A8 2MHz A9 TBZ A10 TAZ B1 B2 B3 B4 B5 B6 B7 B8 MC/SA MCSA0 MCSA3 T/R TXERR TIMERON RTRT COMSTR RD/WR CS MRST RTA3 RTA1 RTPTY RBO RAO ILLCOM DATA1 DATA2 12MHz RTA4 RTA2 RTA0 RBZ RAZ VALMSG Figure 22. UT1760A RTS Pingrid Array Configuration (Bottom View) RTS-35 Package Selection Guide Product BCRT BCRTM BCRTMP RTI 24-pin DIP (single cavity) 36-pin DIP (dual cavity) 68-pin PGA 84-pin PGA 144-pin PGA 84-lead LCC 36-lead FP (dual cavity) (50-mil ctr) 84-lead FP 132-lead FP NOTE: RTMP RTR RTS XCVR X X X X X X X X X1 X X1 X X X X X X 1. 84LCC package is not available radiation-hardened. Packaging-1 D 1.565 0.025 0.080 REF. (2 Places) -A- A 0.130 MAX. Q 0.050 0.010 L 0.130 0.010 A 0.040 REF. E 1.565 0.025 -B- 0.100 REF. (4 Places) PIN 1 I.D. (Geometry Optional) e 0.100 TYP. R P N M L K J H G F E D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 PIN 1 I.D. (Geometry Optional) TOP VIEW -CA (Base Plane) b 0.018 0.002 0.030 C A B 0.010 C 2 SIDE VIEW 1 D1/E1 1.400 BOTTOM VIEW 0.003 MIN. TYP. Notes: 1. True position applies to pins at base plane (datum C). 2. True position applies at pin tips. 3. All package finishes are per MIL-M-38510. 4. Letter designations are for cross-reference to MIL-M-38510. 144-Pin Pingrid Array Packaging-2 D/E 1.525 0.015 SQ. D1/E1 0.950 0.015 SQ. PIN 1 I.D. (Geometry Optional) e 0.025 A 0.110 0.006 A SEE DETAIL A LEAD KOVAR TOP VIEW S1 0.005 MIN. TYP. L 0.250 MIN. REF. A C 0.005 + 0.002 - 0.001 SIDE VIEW 0.014 MAX. REF. (At Braze Pads) DETAIL A 0.018 MAX. REF. BOTTOM VIEW A-A Notes: 1. All package finishes are per MIL-M-38510. 2. Letter designations are for cross-reference to MIL-M-38510. 132-Lead Flatpack (25-MIL Lead Spacing) Packaging-3 D/E 1.150 0.015 SQ. A 0.115 MAX. A1 0.080 0.008 A PIN 1 I.D. (Geometry Optional) TOP VIEW A SIDE VIEW L/L1 0.050 0.005 TYP. h 0.040 x 45_ REF. (3 Places) B1 0.025 0.003 e 0.050 J 0.020 X 455 REF. e1 0.015 MIN. PIN 1 I.D. (Geometry Optional) BOTTOM VIEW A-A Notes: 1. All package finishes are per MIL-M-38510. 2. Letter designations are for cross-reference to MIL-M-38510. 84-LCC Packaging-4 D/E 1.810 0.015 SQ. D1/E1 1.150 0.012 SQ. A 0.110 0.060 PIN 1 I.D. (Geometry Optional) A e 0.050 b 0.016 0.002 SEE DETAIL A A LEAD KOVAR TOP VIEW L 0.260 MIN. REF. C 0.007 0.001 SIDE VIEW S1 0.005 MIN. TYP. 0.018 MAX. REF. 0.014 MAX. REF. (At Braze Pads) BOTTOM VIEW A-A Notes: 1. All package finishes are per MIL-M-38510. 2. Letter designations are for cross-reference to MIL-M-38510. DETAIL A 84-Lead Flatpack (50-MIL Lead Spacing) Packaging-5 D 1.100 0.020 -A- A 0.130 MAX. Q 0.050 0.010 A L 0.130 0.010 E 1.100 0.020 -B- PIN 1 I.D. (Geometry Optional) TOP VIEW -C(Base Plane) e 0.100 TYP. L K J H G D1/ F E D 1.000 A b 0.018 0.002 0.030 C A B 0.010 C 2 SIDE VIEW 1 PIN 1 I.D. (Geometry Optional) BOTTOM VIEW A-A 1 2 3 4 5 6 7 8 9 10 11 0.003 MIN. Notes: 1. True position applies to pins at base plane (datum C). 2. True position applies at pin tips. 3. All packages finishes are per MIL-M-38510. 4. Letter designations are for cross-reference to MIL-M-38510. 84-Pin Pingrid Array Packaging-6 D 1.100 0.020 -A- A 0.130 MAX. Q 0.050 0.010 A L 0.130 0.010 E 1.100 0.020 -B- PIN 1 I.D. (Geometry Optional) TOP e 0.100 TYP. -C(Base Plane) A b 0.010 0.002 0.030 C A B 0.010 C 2 SIDE VIEW 1 L K J H G F E D C B A 123456 PIN 1 I.D. (Geometry Optional) 7 8 9 10 11 D1/E1 1.00 0.003 MIN. TYP. BOTTOM VIEW A-A Notes: 1 True position applies to pins at base plane (datum C). 2 True position applies at pin tips. 3. All packages finishes are per MIL-M-38510. 4. Letter designations are for cross-reference to MIL-M-38510. 68-Pin Pingrid Array Packaging-7 E 0.750 0.015 L 0.490 MIN. b 0.015 0.002 D 1.800 0.025 e 0.10 PIN 1 I.D. (Geometry Optional) TOP VIEW c 0.008 A 0.130 MAX. END VIEW Notes: 1 All package finishes are per MIL-M-38510. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-M-38510. + 0.002 - 0.001 Q 0.080 0.010 (At Ceramic Body) 36-Lead Flatpack, Dual Cavity (100-MIL Lead Spacing) Packaging-8 E 0.700 + 0.015 L 0.330 MIN. b 0.016 + 0.002 D 1.000 0.025 e 0.050 PIN 1 I.D (Geometry Optional) TOP + 0.002 c 0.007 - 0.001 A 0.100 MAX. Q 0.070 + 0.010 (At Ceramic Body) END Notes: 1. All package finishes are per MIL-M-38510. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-M-38510. 36-Lead Flatpack, Dual Cavity (50-MIL Lead Spacing) Packaging-9 E 0.590 0.012 S1 0.005 MIN. S2 0.005 MAX. e 0.100 D 1.800 0.025 b 0.018 0.002 PIN 1 I.D. (Geometry Optional) TOP VIEW A 0.155 MAX. SIDE VIEW L/L1 0.150 MIN. C 0.010 +- 0.002 0.001 E1 0.600 + 0.010 (At Seating Plane) END VIEW Notes: 1. All package finishes are per MIL-M-38510. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-M-38510. 36-Lead Side-Brazed DIP, Dual Cavity Packaging-10 E 0.590 0.015 S1 0.005 MIN. S2 0.005 MAX. e 0.100 D 1.200 0.025 b 0.018 0.002 PIN 1 I.D. (Geometry Optional) A 0.140 MAX. SIDE VIEW L/L1 0.150 MIN. TOP VIEW + 0.002 C 0.010 - 0.001 E1 0.600 + 0.010 (At Seating Plane) Notes: 1. All package finishes are per MIL-M-38510. 2. It is recommended that package ceramic be mounted to a heat removal rail located on the printed circuit board. A thermally conductive material such as MERECO XLN-589 or equivalent should be used. 3. Letter designations are for cross-reference to MIL-M-38510. END VIEW 24-Lead Side-Brazed DIP, Single Cavity Packaging-11 ORDERING INFORMATION UT1553B RTS Remote Terminal for Stores: S 5962 * * * * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Case Outline: (X) = 68 pin PGA Class Designator: (-) = Blank or No field is QML Q Drawing Number: 8957501 Total Dose: (-) = None Federal Stock Class Designator: No options Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. For QML Q product, the Q designator is intentionally left blank in the SMD number (e.g. 5962-8957501XC). UT1553B RTS Remote Terminal for Stores No UT Part Number- * * Lead Finish: (A) = Solder (C) = Gold (X) = Optional Package Type: (G) = 68 pin PGA UTMC Core Part Number Notes: 1. Lead finish (A, C, or X) must be specified. 2. If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). |
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